1. Field of the Invention
An embodiment of the present invention relates to microelectronic device fabrication. In particular, an embodiment of the present invention relates to utilizing multiple material removal steps in a poly open polish process.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages.
These transistors are usually metal oxide semiconductor field effect transistors (MOSFET), which are generally made with metal gate electrodes, as will be understood to those skilled in the art. However, because metal can be difficult to etch with sufficient control of critical dimensions and with sufficient selectivity to an underlying gate oxide, a polysilicon gate electrode can be used for the formation of self-aligned sources and drains and for the formation of a microelectronic transistor. In the formation of a microelectronic transistor, at least one dielectric layer is deposited over the microelectronic transistor structure that has a polysilicon gate electrode. The dielectric layer(s) is planarized, such as by a chemical mechanical polish (CMP), down to and exposing the polysilicon gate. This process is called a poly open polish process. The polysilicon gate electrode may then be removed and replaced by a metal electrode (general also replacing the gate oxide with a high-K dielectric layer) having desirable electrical characteristics, or replaced with new polysilicon which may be salicided to achieved desirable electrical characteristics. Additionally, the existing polysilicon gate may simply be salicided after the polysilicon gate is exposed.
Currently, the CMP technique used in the poly open process utilizes a single slurry and single polishing platen to remove the dielectric layer(s) and other layers (such as an etch stop layer(s) and hard mask(s)) to expose the polysilicon gate. The single slurry/single platen process is dependent upon dielectric layer uniformity, polisher hardware variations, and polish rate variations caused by consumable variations. Furthermore, there is no endpoint with the single slurry/single platen process.
The lack of control with the poly open process is a problem because the dimensions (e.g., height) of the transistor gate must be substantially consistent within each device (WID) to have a properly functioning device, within the wafer (WIW) to have consistent performance between devices formed on each microelectronic wafer, and from wafer to wafer (WTW) to have consistent performance across all devices produced.
Therefore, it would be advantageous to develop a poly open process which has greater control over the WID uniformity, WIW uniformity, and WTW uniformity.